1. Field of the Invention
The present invention relates to a power source system used in a camera, and in particular, to a power source system that permits a digital logic circuit within the camera to be reset consistently.
2. Description of Related Art
In cameras in general, a battery is used as a power source, and a DC/DC converter is used in order to supply power from this battery to circuit blocks in a consistent manner. In addition, a conventional camera includes digital circuits that process digital signals and analog circuits that process analog signals. Correspondingly, power source systems are also divided into analog power sources and digital power sources, depending on the type of signal processed. Typically, power for both the analog power source and the digital power source is output from a single DC/DC converter. Accordingly, the output of each source of power is turned on and off with the same timing.
FIG. 6 is a block diagram of such a conventional power source circuit. The FIG. 6 circuit includes a battery 1, a DC/DC converter 2, a logic reset circuit 3, a logic circuit 4 and a CPU 5.
When the battery 1 is installed in the camera, power is supplied to the CPU 5, and the CPU 5 enters an operating state. In this case, the CPU 5 outputs an "L" level control signal CTL to a control terminal CNT of the DC/DC converter 2 and starts the DC/DC converter 2. When this occurs, voltage is output from a 5 V output terminal OUT of the DC/DC converter 2. This power is supplied as VCC to the logic circuit 4 and as AVCC to the logic reset circuit 3 that resets the logic circuit 4.
FIG. 7 is a drawing showing the voltage waveforms for each part of the power source system when battery power is supplied.
The analog-type logic reset circuit 3 resets the digital logic circuit 4. The logic reset circuit 3 receives the power supplied to the logic circuit 4 via a terminal MON. The logic circuit 4 is driven by a digital power source. Accordingly, the output of the logic reset circuit 3, which is an analog circuit, rises with the same timing as the power supplied to the logic circuit 4, which is a digital circuit. Consequently, when the power supplied to the logic circuit 4 is not constant, e.g., while the power level is rising, a proper reset condition cannot be maintained because the logic reset circuit 3 is receiving a non-constant signal. FIGS. 7b and 7c illustrate this problem by showing that the signal (FIG. 7c) received by logic reset circuit 3 varies with the signal output by DC/DC converter 2. Therefore, the logic system of the prior art cannot be initialized with certainty.
As a result, when the output level of the logic circuit 4 is the output wave form of a MOS open drain-type for instance, if the logic circuit 4 is initialized normally, the circuit should be in the OFF state (i.e., the default state). If the logic circuit 4 is not initialized normally, however, the transistors at the output level become ON, causing erroneous operations, e.g., sinking current.